Fast Implementation of Lifting based 1D/2D/3D DWT-IDWT Architecture for Image Compression

Technological growth in semiconductor industry have led to unprecedented demand for faster, area efficient and low power VLSI circuits for complex image processing applications. DWT-IDWT is one of the most popular IP that is used for image transformation. In this work, a high speed, low power DWT/IDWT architecture is designed and implemented on ASIC using 130nm Technology. 2D DWT architecture based on lifting scheme architecture uses multipliers and adders, thus consuming power. This paper addresses power reduction in multiplier by proposing a modified algorithm for BZFAD multiplier. The proposed BZFAD multiplier is 65% faster and occupies 44% less area compared with the generic multipliers. The DWT architecture designed based on modified BZFAD multiplier achieves 35% less power reduction and operates at frequency of 200MHz with latency of 1536 clock cycles for 512x512 images. The 3D-DWT architecture is designed for 8x8x8 video frame, based on fast lifting scheme approach using (9, 7) wavelet filter. Using 9/7 filter for DWT computation reduces the hardware complexity, memory accesses and achieves minimum error in reconstruction of images. The proposed architecture systematically combines hardware optimization techniques to develop a flexible DWT architecture that has high performance and is suitable for portable, high speed, low power applications. 3D-DWT architecture has been implemented on Virtex-5 FPGA with utilization of 1,152 out of 19,200(5%) slice registers and the frequency of operation is 256.